diff options
Diffstat (limited to 'ffmpeg/libavcodec/sparc/vis.h')
| -rw-r--r-- | ffmpeg/libavcodec/sparc/vis.h | 105 |
1 files changed, 19 insertions, 86 deletions
diff --git a/ffmpeg/libavcodec/sparc/vis.h b/ffmpeg/libavcodec/sparc/vis.h index adee91b..107ff96 100644 --- a/ffmpeg/libavcodec/sparc/vis.h +++ b/ffmpeg/libavcodec/sparc/vis.h @@ -42,6 +42,17 @@ #ifndef AVCODEC_SPARC_VIS_H #define AVCODEC_SPARC_VIS_H +#define ACCEL_SPARC_VIS 1 +#define ACCEL_SPARC_VIS2 2 + +static inline int vis_level(void) +{ + int accel = 0; + accel |= ACCEL_SPARC_VIS; + accel |= ACCEL_SPARC_VIS2; + return accel; +} + #define vis_opc_base ((0x1 << 31) | (0x36 << 19)) #define vis_opf(X) ((X) << 5) #define vis_sreg(X) (X) @@ -139,12 +150,9 @@ #define vis_m2r_2(op,mem1,mem2,rd) \ __asm__ volatile (#op "\t[%0 + %1], %%f" #rd : : "r" (mem1), "r" (mem2) ) -static inline void vis_set_gsr(unsigned int _val) +static inline void vis_set_gsr(unsigned int val) { - register unsigned int val __asm__("g1"); - - val = _val; - __asm__ volatile(".word 0xa7804000" + __asm__ volatile("mov %0,%%asr19" : : "r" (val)); } @@ -162,32 +170,6 @@ static inline void vis_set_gsr(unsigned int _val) #define vis_st64(rs1,mem) vis_r2m(std, rs1, mem) #define vis_st64_2(rs1,mem1,mem2) vis_r2m_2(std, rs1, mem1, mem2) -#define vis_ldblk(mem, rd) \ -do { register void *__mem __asm__("g1"); \ - __mem = &(mem); \ - __asm__ volatile(".word 0xc1985e00 | %1" \ - : \ - : "r" (__mem), \ - "i" (vis_rd_d(rd)) \ - : "memory"); \ -} while (0) - -#define vis_stblk(rd, mem) \ -do { register void *__mem __asm__("g1"); \ - __mem = &(mem); \ - __asm__ volatile(".word 0xc1b85e00 | %1" \ - : \ - : "r" (__mem), \ - "i" (vis_rd_d(rd)) \ - : "memory"); \ -} while (0) - -#define vis_membar_storestore() \ - __asm__ volatile(".word 0x8143e008" : : : "memory") - -#define vis_membar_sync() \ - __asm__ volatile(".word 0x8143e040" : : : "memory") - /* 16 and 32 bit partitioned addition and subtraction. The normal * versions perform 4 16-bit or 2 32-bit additions or subtractions. * The 's' versions perform 2 16-bit or 1 32-bit additions or @@ -223,68 +205,19 @@ do { register void *__mem __asm__("g1"); \ /* Alignment instructions. */ -static inline const void *vis_alignaddr(const void *_ptr) +static inline const void *vis_alignaddr(const void *ptr) { - register const void *ptr __asm__("g1"); - - ptr = _ptr; - - __asm__ volatile(".word %2" + __asm__ volatile("alignaddr %0, %%g0, %0" : "=&r" (ptr) - : "0" (ptr), - "i" (vis_opc_base | vis_opf(0x18) | - vis_rs1_s(1) | - vis_rs2_s(0) | - vis_rd_s(1))); + : "0" (ptr)); return ptr; } -static inline void vis_alignaddr_g0(void *_ptr) +static inline void vis_alignaddr_g0(void *ptr) { - register void *ptr __asm__("g1"); - - ptr = _ptr; - - __asm__ volatile(".word %2" - : "=&r" (ptr) - : "0" (ptr), - "i" (vis_opc_base | vis_opf(0x18) | - vis_rs1_s(1) | - vis_rs2_s(0) | - vis_rd_s(0))); -} - -static inline void *vis_alignaddrl(void *_ptr) -{ - register void *ptr __asm__("g1"); - - ptr = _ptr; - - __asm__ volatile(".word %2" - : "=&r" (ptr) - : "0" (ptr), - "i" (vis_opc_base | vis_opf(0x19) | - vis_rs1_s(1) | - vis_rs2_s(0) | - vis_rd_s(1))); - - return ptr; -} - -static inline void vis_alignaddrl_g0(void *_ptr) -{ - register void *ptr __asm__("g1"); - - ptr = _ptr; - - __asm__ volatile(".word %2" - : "=&r" (ptr) - : "0" (ptr), - "i" (vis_opc_base | vis_opf(0x19) | - vis_rs1_s(1) | - vis_rs2_s(0) | - vis_rd_s(0))); + __asm__ volatile("alignaddr %0, %%g0, %%g0" + : : "r" (ptr)); } #define vis_faligndata(rs1,rs2,rd) vis_dd2d(0x48, rs1, rs2, rd) |