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-rw-r--r--ffmpeg/libavutil/x86/Makefile2
-rw-r--r--ffmpeg/libavutil/x86/cpu.c9
-rw-r--r--ffmpeg/libavutil/x86/cpu.h70
-rw-r--r--ffmpeg/libavutil/x86/float_dsp.asm25
-rw-r--r--ffmpeg/libavutil/x86/float_dsp_init.c44
-rw-r--r--ffmpeg/libavutil/x86/timer.h1
-rw-r--r--ffmpeg/libavutil/x86/w64xmmtest.h8
-rw-r--r--ffmpeg/libavutil/x86/x86inc.asm586
-rw-r--r--ffmpeg/libavutil/x86/x86util.asm13
9 files changed, 498 insertions, 260 deletions
diff --git a/ffmpeg/libavutil/x86/Makefile b/ffmpeg/libavutil/x86/Makefile
index ae07470..1e19082 100644
--- a/ffmpeg/libavutil/x86/Makefile
+++ b/ffmpeg/libavutil/x86/Makefile
@@ -1,6 +1,8 @@
OBJS += x86/cpu.o \
x86/float_dsp_init.o \
+ x86/lls_init.o \
YASM-OBJS += x86/cpuid.o \
x86/emms.o \
x86/float_dsp.o \
+ x86/lls.o \
diff --git a/ffmpeg/libavutil/x86/cpu.c b/ffmpeg/libavutil/x86/cpu.c
index a3a5239..18049ea 100644
--- a/ffmpeg/libavutil/x86/cpu.c
+++ b/ffmpeg/libavutil/x86/cpu.c
@@ -26,6 +26,7 @@
#include "libavutil/x86/asm.h"
#include "libavutil/x86/cpu.h"
#include "libavutil/cpu.h"
+#include "libavutil/cpu_internal.h"
#if HAVE_YASM
@@ -133,6 +134,14 @@ int ff_get_cpu_flags_x86(void)
if ((eax & 0x6) == 0x6)
rval |= AV_CPU_FLAG_AVX;
}
+#if HAVE_AVX2
+ if (max_std_level >= 7) {
+ cpuid(7, eax, ebx, ecx, edx);
+ if (ebx&0x00000020)
+ rval |= AV_CPU_FLAG_AVX2;
+ /* TODO: BMI1/2 */
+ }
+#endif /* HAVE_AVX2 */
#endif /* HAVE_AVX */
#endif /* HAVE_SSE */
}
diff --git a/ffmpeg/libavutil/x86/cpu.h b/ffmpeg/libavutil/x86/cpu.h
index 601476e..3724357 100644
--- a/ffmpeg/libavutil/x86/cpu.h
+++ b/ffmpeg/libavutil/x86/cpu.h
@@ -21,38 +21,52 @@
#include "config.h"
#include "libavutil/cpu.h"
-
-#define CPUEXT(flags, suffix, cpuext) \
- (HAVE_ ## cpuext ## suffix && ((flags) & AV_CPU_FLAG_ ## cpuext))
+#include "libavutil/cpu_internal.h"
#define AV_CPU_FLAG_AMD3DNOW AV_CPU_FLAG_3DNOW
#define AV_CPU_FLAG_AMD3DNOWEXT AV_CPU_FLAG_3DNOWEXT
-#define EXTERNAL_AMD3DNOW(flags) CPUEXT(flags, _EXTERNAL, AMD3DNOW)
-#define EXTERNAL_AMD3DNOWEXT(flags) CPUEXT(flags, _EXTERNAL, AMD3DNOWEXT)
-#define EXTERNAL_MMX(flags) CPUEXT(flags, _EXTERNAL, MMX)
-#define EXTERNAL_MMXEXT(flags) CPUEXT(flags, _EXTERNAL, MMXEXT)
-#define EXTERNAL_SSE(flags) CPUEXT(flags, _EXTERNAL, SSE)
-#define EXTERNAL_SSE2(flags) CPUEXT(flags, _EXTERNAL, SSE2)
-#define EXTERNAL_SSE3(flags) CPUEXT(flags, _EXTERNAL, SSE3)
-#define EXTERNAL_SSSE3(flags) CPUEXT(flags, _EXTERNAL, SSSE3)
-#define EXTERNAL_SSE4(flags) CPUEXT(flags, _EXTERNAL, SSE4)
-#define EXTERNAL_SSE42(flags) CPUEXT(flags, _EXTERNAL, SSE42)
-#define EXTERNAL_AVX(flags) CPUEXT(flags, _EXTERNAL, AVX)
-#define EXTERNAL_FMA4(flags) CPUEXT(flags, _EXTERNAL, FMA4)
-
-#define INLINE_AMD3DNOW(flags) CPUEXT(flags, _INLINE, AMD3DNOW)
-#define INLINE_AMD3DNOWEXT(flags) CPUEXT(flags, _INLINE, AMD3DNOWEXT)
-#define INLINE_MMX(flags) CPUEXT(flags, _INLINE, MMX)
-#define INLINE_MMXEXT(flags) CPUEXT(flags, _INLINE, MMXEXT)
-#define INLINE_SSE(flags) CPUEXT(flags, _INLINE, SSE)
-#define INLINE_SSE2(flags) CPUEXT(flags, _INLINE, SSE2)
-#define INLINE_SSE3(flags) CPUEXT(flags, _INLINE, SSE3)
-#define INLINE_SSSE3(flags) CPUEXT(flags, _INLINE, SSSE3)
-#define INLINE_SSE4(flags) CPUEXT(flags, _INLINE, SSE4)
-#define INLINE_SSE42(flags) CPUEXT(flags, _INLINE, SSE42)
-#define INLINE_AVX(flags) CPUEXT(flags, _INLINE, AVX)
-#define INLINE_FMA4(flags) CPUEXT(flags, _INLINE, FMA4)
+#define X86_AMD3DNOW(flags) CPUEXT(flags, AMD3DNOW)
+#define X86_AMD3DNOWEXT(flags) CPUEXT(flags, AMD3DNOWEXT)
+#define X86_MMX(flags) CPUEXT(flags, MMX)
+#define X86_MMXEXT(flags) CPUEXT(flags, MMXEXT)
+#define X86_SSE(flags) CPUEXT(flags, SSE)
+#define X86_SSE2(flags) CPUEXT(flags, SSE2)
+#define X86_SSE3(flags) CPUEXT(flags, SSE3)
+#define X86_SSSE3(flags) CPUEXT(flags, SSSE3)
+#define X86_SSE4(flags) CPUEXT(flags, SSE4)
+#define X86_SSE42(flags) CPUEXT(flags, SSE42)
+#define X86_AVX(flags) CPUEXT(flags, AVX)
+#define X86_FMA4(flags) CPUEXT(flags, FMA4)
+#define X86_AVX2(flags) CPUEXT(flags, AVX2)
+
+#define EXTERNAL_AMD3DNOW(flags) CPUEXT_SUFFIX(flags, _EXTERNAL, AMD3DNOW)
+#define EXTERNAL_AMD3DNOWEXT(flags) CPUEXT_SUFFIX(flags, _EXTERNAL, AMD3DNOWEXT)
+#define EXTERNAL_MMX(flags) CPUEXT_SUFFIX(flags, _EXTERNAL, MMX)
+#define EXTERNAL_MMXEXT(flags) CPUEXT_SUFFIX(flags, _EXTERNAL, MMXEXT)
+#define EXTERNAL_SSE(flags) CPUEXT_SUFFIX(flags, _EXTERNAL, SSE)
+#define EXTERNAL_SSE2(flags) CPUEXT_SUFFIX(flags, _EXTERNAL, SSE2)
+#define EXTERNAL_SSE3(flags) CPUEXT_SUFFIX(flags, _EXTERNAL, SSE3)
+#define EXTERNAL_SSSE3(flags) CPUEXT_SUFFIX(flags, _EXTERNAL, SSSE3)
+#define EXTERNAL_SSE4(flags) CPUEXT_SUFFIX(flags, _EXTERNAL, SSE4)
+#define EXTERNAL_SSE42(flags) CPUEXT_SUFFIX(flags, _EXTERNAL, SSE42)
+#define EXTERNAL_AVX(flags) CPUEXT_SUFFIX(flags, _EXTERNAL, AVX)
+#define EXTERNAL_FMA4(flags) CPUEXT_SUFFIX(flags, _EXTERNAL, FMA4)
+#define EXTERNAL_AVX2(flags) CPUEXT_SUFFIX(flags, _EXTERNAL, AVX2)
+
+#define INLINE_AMD3DNOW(flags) CPUEXT_SUFFIX(flags, _INLINE, AMD3DNOW)
+#define INLINE_AMD3DNOWEXT(flags) CPUEXT_SUFFIX(flags, _INLINE, AMD3DNOWEXT)
+#define INLINE_MMX(flags) CPUEXT_SUFFIX(flags, _INLINE, MMX)
+#define INLINE_MMXEXT(flags) CPUEXT_SUFFIX(flags, _INLINE, MMXEXT)
+#define INLINE_SSE(flags) CPUEXT_SUFFIX(flags, _INLINE, SSE)
+#define INLINE_SSE2(flags) CPUEXT_SUFFIX(flags, _INLINE, SSE2)
+#define INLINE_SSE3(flags) CPUEXT_SUFFIX(flags, _INLINE, SSE3)
+#define INLINE_SSSE3(flags) CPUEXT_SUFFIX(flags, _INLINE, SSSE3)
+#define INLINE_SSE4(flags) CPUEXT_SUFFIX(flags, _INLINE, SSE4)
+#define INLINE_SSE42(flags) CPUEXT_SUFFIX(flags, _INLINE, SSE42)
+#define INLINE_AVX(flags) CPUEXT_SUFFIX(flags, _INLINE, AVX)
+#define INLINE_FMA4(flags) CPUEXT_SUFFIX(flags, _INLINE, FMA4)
+#define INLINE_AVX2(flags) CPUEXT_SUFFIX(flags, _INLINE, AVX2)
void ff_cpu_cpuid(int index, int *eax, int *ebx, int *ecx, int *edx);
void ff_cpu_xgetbv(int op, int *eax, int *edx);
diff --git a/ffmpeg/libavutil/x86/float_dsp.asm b/ffmpeg/libavutil/x86/float_dsp.asm
index 004e6cf..49d4876 100644
--- a/ffmpeg/libavutil/x86/float_dsp.asm
+++ b/ffmpeg/libavutil/x86/float_dsp.asm
@@ -263,3 +263,28 @@ cglobal scalarproduct_float, 3,3,2, v1, v2, offset
%endif
RET
+;-----------------------------------------------------------------------------
+; void ff_butterflies_float(float *src0, float *src1, int len);
+;-----------------------------------------------------------------------------
+INIT_XMM sse
+cglobal butterflies_float, 3,3,3, src0, src1, len
+%if ARCH_X86_64
+ movsxd lenq, lend
+%endif
+ test lenq, lenq
+ jz .end
+ shl lenq, 2
+ add src0q, lenq
+ add src1q, lenq
+ neg lenq
+.loop:
+ mova m0, [src0q + lenq]
+ mova m1, [src1q + lenq]
+ subps m2, m0, m1
+ addps m0, m0, m1
+ mova [src1q + lenq], m2
+ mova [src0q + lenq], m0
+ add lenq, mmsize
+ jl .loop
+.end:
+ REP_RET
diff --git a/ffmpeg/libavutil/x86/float_dsp_init.c b/ffmpeg/libavutil/x86/float_dsp_init.c
index 5c6383b..97f7b7c 100644
--- a/ffmpeg/libavutil/x86/float_dsp_init.c
+++ b/ffmpeg/libavutil/x86/float_dsp_init.c
@@ -18,28 +18,29 @@
#include "config.h"
+#include "libavutil/attributes.h"
#include "libavutil/cpu.h"
#include "libavutil/float_dsp.h"
#include "cpu.h"
#include "asm.h"
-extern void ff_vector_fmul_sse(float *dst, const float *src0, const float *src1,
+void ff_vector_fmul_sse(float *dst, const float *src0, const float *src1,
+ int len);
+void ff_vector_fmul_avx(float *dst, const float *src0, const float *src1,
+ int len);
+
+void ff_vector_fmac_scalar_sse(float *dst, const float *src, float mul,
int len);
-extern void ff_vector_fmul_avx(float *dst, const float *src0, const float *src1,
+void ff_vector_fmac_scalar_avx(float *dst, const float *src, float mul,
int len);
-extern void ff_vector_fmac_scalar_sse(float *dst, const float *src, float mul,
- int len);
-extern void ff_vector_fmac_scalar_avx(float *dst, const float *src, float mul,
- int len);
-
-extern void ff_vector_fmul_scalar_sse(float *dst, const float *src, float mul,
- int len);
+void ff_vector_fmul_scalar_sse(float *dst, const float *src, float mul,
+ int len);
-extern void ff_vector_dmul_scalar_sse2(double *dst, const double *src,
- double mul, int len);
-extern void ff_vector_dmul_scalar_avx(double *dst, const double *src,
- double mul, int len);
+void ff_vector_dmul_scalar_sse2(double *dst, const double *src,
+ double mul, int len);
+void ff_vector_dmul_scalar_avx(double *dst, const double *src,
+ double mul, int len);
void ff_vector_fmul_add_sse(float *dst, const float *src0, const float *src1,
const float *src2, int len);
@@ -53,6 +54,8 @@ void ff_vector_fmul_reverse_avx(float *dst, const float *src0,
float ff_scalarproduct_float_sse(const float *v1, const float *v2, int order);
+void ff_butterflies_float_sse(float *src0, float *src1, int len);
+
#if HAVE_6REGS && HAVE_INLINE_ASM
static void vector_fmul_window_3dnowext(float *dst, const float *src0,
const float *src1, const float *win,
@@ -119,30 +122,31 @@ static void vector_fmul_window_sse(float *dst, const float *src0,
}
#endif /* HAVE_6REGS && HAVE_INLINE_ASM */
-void ff_float_dsp_init_x86(AVFloatDSPContext *fdsp)
+av_cold void ff_float_dsp_init_x86(AVFloatDSPContext *fdsp)
{
- int mm_flags = av_get_cpu_flags();
+ int cpu_flags = av_get_cpu_flags();
#if HAVE_6REGS && HAVE_INLINE_ASM
- if (INLINE_AMD3DNOWEXT(mm_flags)) {
+ if (INLINE_AMD3DNOWEXT(cpu_flags)) {
fdsp->vector_fmul_window = vector_fmul_window_3dnowext;
}
- if (INLINE_SSE(mm_flags)) {
+ if (INLINE_SSE(cpu_flags)) {
fdsp->vector_fmul_window = vector_fmul_window_sse;
}
#endif
- if (EXTERNAL_SSE(mm_flags)) {
+ if (EXTERNAL_SSE(cpu_flags)) {
fdsp->vector_fmul = ff_vector_fmul_sse;
fdsp->vector_fmac_scalar = ff_vector_fmac_scalar_sse;
fdsp->vector_fmul_scalar = ff_vector_fmul_scalar_sse;
fdsp->vector_fmul_add = ff_vector_fmul_add_sse;
fdsp->vector_fmul_reverse = ff_vector_fmul_reverse_sse;
fdsp->scalarproduct_float = ff_scalarproduct_float_sse;
+ fdsp->butterflies_float = ff_butterflies_float_sse;
}
- if (EXTERNAL_SSE2(mm_flags)) {
+ if (EXTERNAL_SSE2(cpu_flags)) {
fdsp->vector_dmul_scalar = ff_vector_dmul_scalar_sse2;
}
- if (EXTERNAL_AVX(mm_flags)) {
+ if (EXTERNAL_AVX(cpu_flags)) {
fdsp->vector_fmul = ff_vector_fmul_avx;
fdsp->vector_fmac_scalar = ff_vector_fmac_scalar_avx;
fdsp->vector_dmul_scalar = ff_vector_dmul_scalar_avx;
diff --git a/ffmpeg/libavutil/x86/timer.h b/ffmpeg/libavutil/x86/timer.h
index 5969876..d812d46 100644
--- a/ffmpeg/libavutil/x86/timer.h
+++ b/ffmpeg/libavutil/x86/timer.h
@@ -36,6 +36,7 @@ static inline uint64_t read_time(void)
#elif HAVE_RDTSC
+#include <intrin.h>
#define AV_READ_TIME __rdtsc
#endif /* HAVE_INLINE_ASM */
diff --git a/ffmpeg/libavutil/x86/w64xmmtest.h b/ffmpeg/libavutil/x86/w64xmmtest.h
index b4ce7d3..9df499f 100644
--- a/ffmpeg/libavutil/x86/w64xmmtest.h
+++ b/ffmpeg/libavutil/x86/w64xmmtest.h
@@ -2,20 +2,20 @@
* check XMM registers for clobbers on Win64
* Copyright (c) 2008 Ramiro Polla <ramiro.polla@gmail.com>
*
- * This file is part of Libav.
+ * This file is part of FFmpeg.
*
- * Libav is free software; you can redistribute it and/or
+ * FFmpeg is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
- * Libav is distributed in the hope that it will be useful,
+ * FFmpeg is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
- * License along with Libav; if not, write to the Free Software
+ * License along with FFmpeg; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
diff --git a/ffmpeg/libavutil/x86/x86inc.asm b/ffmpeg/libavutil/x86/x86inc.asm
index 068e3cf..420e293 100644
--- a/ffmpeg/libavutil/x86/x86inc.asm
+++ b/ffmpeg/libavutil/x86/x86inc.asm
@@ -1,12 +1,12 @@
;*****************************************************************************
;* x86inc.asm: x264asm abstraction layer
;*****************************************************************************
-;* Copyright (C) 2005-2012 x264 project
+;* Copyright (C) 2005-2013 x264 project
;*
;* Authors: Loren Merritt <lorenm@u.washington.edu>
;* Anton Mitrofanov <BugMaster@narod.ru>
;* Jason Garrett-Glaser <darkshikari@gmail.com>
-;* Henrik Gramner <hengar-6@student.ltu.se>
+;* Henrik Gramner <henrik@gramner.com>
;*
;* Permission to use, copy, modify, and/or distribute this software for any
;* purpose with or without fee is hereby granted, provided that the above
@@ -49,6 +49,8 @@
%define WIN64 1
%elifidn __OUTPUT_FORMAT__,win64
%define WIN64 1
+ %elifidn __OUTPUT_FORMAT__,x64
+ %define WIN64 1
%else
%define UNIX64 1
%endif
@@ -60,42 +62,17 @@
%define mangle(x) x
%endif
-; Name of the .rodata section.
+; aout does not support align=
+; NOTE: This section is out of sync with x264, in order to
+; keep supporting OS/2.
%macro SECTION_RODATA 0-1 16
- ; Kludge: Something on OS X fails to align .rodata even given an align
- ; attribute, so use a different read-only section. This has been fixed in
- ; yasm 0.8.0 and nasm 2.6.
- %ifdef __YASM_VERSION_ID__
- %if __YASM_VERSION_ID__ < 00080000h
- %define NEED_MACHO_RODATA_KLUDGE
- %endif
- %elifdef __NASM_VERSION_ID__
- %if __NASM_VERSION_ID__ < 02060000h
- %define NEED_MACHO_RODATA_KLUDGE
- %endif
- %endif
-
%ifidn __OUTPUT_FORMAT__,aout
section .text
%else
- %ifndef NEED_MACHO_RODATA_KLUDGE
- SECTION .rodata align=%1
- %else
- %ifidn __OUTPUT_FORMAT__,macho64
- SECTION .text align=%1
- %elifidn __OUTPUT_FORMAT__,macho
- SECTION .text align=%1
- fakegot:
- %else
- SECTION .rodata align=%1
- %endif
- %endif
+ SECTION .rodata align=%1
%endif
-
- %undef NEED_MACHO_RODATA_KLUDGE
%endmacro
-; aout does not support align=
%macro SECTION_TEXT 0-1 16
%ifidn __OUTPUT_FORMAT__,aout
SECTION .text
@@ -154,8 +131,7 @@ CPUNOP amdnop
; Pops anything that was pushed by PROLOGUE, and returns.
; REP_RET:
-; Same, but if it doesn't pop anything it becomes a 2-byte ret, for athlons
-; which are slow when a normal ret follows a branch.
+; Use this instead of RET if it's a branch target.
; registers:
; rN and rNq are the native-size register holding function argument N
@@ -354,14 +330,18 @@ DECLARE_REG_TMP_SIZE 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14
%if stack_size < 0
%assign stack_size -stack_size
%endif
- %if mmsize != 8
- %assign xmm_regs_used %2
+ %assign stack_size_padded stack_size
+ %if WIN64
+ %assign stack_size_padded stack_size_padded + 32 ; reserve 32 bytes for shadow space
+ %if mmsize != 8
+ %assign xmm_regs_used %2
+ %if xmm_regs_used > 8
+ %assign stack_size_padded stack_size_padded + (xmm_regs_used-8)*16
+ %endif
+ %endif
%endif
%if mmsize <= 16 && HAVE_ALIGNED_STACK
- %assign stack_size_padded stack_size + %%stack_alignment - gprsize - (stack_offset & (%%stack_alignment - 1))
- %if xmm_regs_used > 6
- %assign stack_size_padded stack_size_padded + (xmm_regs_used - 6) * 16
- %endif
+ %assign stack_size_padded stack_size_padded + %%stack_alignment - gprsize - (stack_offset & (%%stack_alignment - 1))
SUB rsp, stack_size_padded
%else
%assign %%reg_num (regs_used - 1)
@@ -371,14 +351,6 @@ DECLARE_REG_TMP_SIZE 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14
; stack in a single instruction (i.e. mov rsp, rstk or mov
; rsp, [rsp+stack_size_padded])
mov rstk, rsp
- %assign stack_size_padded stack_size
- %if xmm_regs_used > 6
- %assign stack_size_padded stack_size_padded + (xmm_regs_used - 6) * 16
- %if mmsize == 32 && xmm_regs_used & 1
- ; re-align to 32 bytes
- %assign stack_size_padded (stack_size_padded + 16)
- %endif
- %endif
%if %1 < 0 ; need to store rsp on stack
sub rsp, gprsize+stack_size_padded
and rsp, ~(%%stack_alignment-1)
@@ -390,9 +362,7 @@ DECLARE_REG_TMP_SIZE 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14
%xdefine rstkm rstk
%endif
%endif
- %if xmm_regs_used > 6
- WIN64_PUSH_XMM
- %endif
+ WIN64_PUSH_XMM
%endif
%endif
%endmacro
@@ -453,40 +423,55 @@ DECLARE_REG 14, R15, 120
%endmacro
%macro WIN64_PUSH_XMM 0
- %assign %%i xmm_regs_used
- %rep (xmm_regs_used-6)
- %assign %%i %%i-1
- movdqa [rsp + (%%i-6)*16 + stack_size + (~stack_offset&8)], xmm %+ %%i
- %endrep
+ ; Use the shadow space to store XMM6 and XMM7, the rest needs stack space allocated.
+ %if xmm_regs_used > 6
+ movaps [rstk + stack_offset + 8], xmm6
+ %endif
+ %if xmm_regs_used > 7
+ movaps [rstk + stack_offset + 24], xmm7
+ %endif
+ %if xmm_regs_used > 8
+ %assign %%i 8
+ %rep xmm_regs_used-8
+ movaps [rsp + (%%i-8)*16 + stack_size + 32], xmm %+ %%i
+ %assign %%i %%i+1
+ %endrep
+ %endif
%endmacro
%macro WIN64_SPILL_XMM 1
%assign xmm_regs_used %1
ASSERT xmm_regs_used <= 16
- %if xmm_regs_used > 6
- SUB rsp, (xmm_regs_used-6)*16+16
- WIN64_PUSH_XMM
+ %if xmm_regs_used > 8
+ %assign stack_size_padded (xmm_regs_used-8)*16 + (~stack_offset&8) + 32
+ SUB rsp, stack_size_padded
%endif
+ WIN64_PUSH_XMM
%endmacro
%macro WIN64_RESTORE_XMM_INTERNAL 1
- %if xmm_regs_used > 6
+ %assign %%pad_size 0
+ %if xmm_regs_used > 8
%assign %%i xmm_regs_used
- %rep (xmm_regs_used-6)
+ %rep xmm_regs_used-8
%assign %%i %%i-1
- movdqa xmm %+ %%i, [%1 + (%%i-6)*16+stack_size+(~stack_offset&8)]
+ movaps xmm %+ %%i, [%1 + (%%i-8)*16 + stack_size + 32]
%endrep
- %if stack_size_padded == 0
- add %1, (xmm_regs_used-6)*16+16
- %endif
%endif
%if stack_size_padded > 0
%if stack_size > 0 && (mmsize == 32 || HAVE_ALIGNED_STACK == 0)
mov rsp, rstkm
%else
add %1, stack_size_padded
+ %assign %%pad_size stack_size_padded
%endif
%endif
+ %if xmm_regs_used > 7
+ movaps xmm7, [%1 + stack_offset - %%pad_size + 24]
+ %endif
+ %if xmm_regs_used > 6
+ movaps xmm6, [%1 + stack_offset - %%pad_size + 8]
+ %endif
%endmacro
%macro WIN64_RESTORE_XMM 1
@@ -503,7 +488,7 @@ DECLARE_REG 14, R15, 120
%if mmsize == 32
vzeroupper
%endif
- ret
+ AUTO_REP_RET
%endmacro
%elif ARCH_X86_64 ; *nix x64 ;=============================================
@@ -550,7 +535,7 @@ DECLARE_REG 14, R15, 72
%if mmsize == 32
vzeroupper
%endif
- ret
+ AUTO_REP_RET
%endmacro
%else ; X86_32 ;==============================================================
@@ -606,7 +591,7 @@ DECLARE_ARG 7, 8, 9, 10, 11, 12, 13, 14
%if mmsize == 32
vzeroupper
%endif
- ret
+ AUTO_REP_RET
%endmacro
%endif ;======================================================================
@@ -620,6 +605,10 @@ DECLARE_ARG 7, 8, 9, 10, 11, 12, 13, 14
%endmacro
%endif
+; On AMD cpus <=K10, an ordinary ret is slow if it immediately follows either
+; a branch or a branch target. So switch to a 2-byte form of ret in that case.
+; We can automatically detect "follows a branch", but not a branch target.
+; (SSSE3 is a sufficient condition to know that your cpu doesn't have this problem.)
%macro REP_RET 0
%if has_epilogue
RET
@@ -628,6 +617,29 @@ DECLARE_ARG 7, 8, 9, 10, 11, 12, 13, 14
%endif
%endmacro
+%define last_branch_adr $$
+%macro AUTO_REP_RET 0
+ %ifndef cpuflags
+ times ((last_branch_adr-$)>>31)+1 rep ; times 1 iff $ != last_branch_adr.
+ %elif notcpuflag(ssse3)
+ times ((last_branch_adr-$)>>31)+1 rep
+ %endif
+ ret
+%endmacro
+
+%macro BRANCH_INSTR 0-*
+ %rep %0
+ %macro %1 1-2 %1
+ %2 %1
+ %%branch_instr:
+ %xdefine last_branch_adr %%branch_instr
+ %endmacro
+ %rotate 1
+ %endrep
+%endmacro
+
+BRANCH_INSTR jz, je, jnz, jne, jl, jle, jnl, jnle, jg, jge, jng, jnge, ja, jae, jna, jnae, jb, jbe, jnb, jnbe, jc, jnc, js, jns, jo, jno, jp, jnp
+
%macro TAIL_CALL 2 ; callee, is_nonadjacent
%if has_epilogue
call %1
@@ -676,12 +688,12 @@ DECLARE_ARG 7, 8, 9, 10, 11, 12, 13, 14
%endif
align function_align
%2:
- RESET_MM_PERMUTATION ; not really needed, but makes disassembly somewhat nicer
- %xdefine rstk rsp
- %assign stack_offset 0
- %assign stack_size 0
- %assign stack_size_padded 0
- %assign xmm_regs_used 0
+ RESET_MM_PERMUTATION ; needed for x86-64, also makes disassembly somewhat nicer
+ %xdefine rstk rsp ; copy of the original stack pointer, used when greater alignment than the known stack alignment is required
+ %assign stack_offset 0 ; stack pointer offset relative to the return address
+ %assign stack_size 0 ; amount of stack space that can be freely used inside a function
+ %assign stack_size_padded 0 ; total amount of allocated stack space, including space for callee-saved xmm registers on WIN64 and alignment padding
+ %assign xmm_regs_used 0 ; number of XMM registers requested, used for dealing with callee-saved registers on WIN64
%ifnidn %3, ""
PROLOGUE %3
%endif
@@ -700,9 +712,13 @@ DECLARE_ARG 7, 8, 9, 10, 11, 12, 13, 14
extern %1
%endmacro
-%macro const 2+
+%macro const 1-2+
%xdefine %1 mangle(private_prefix %+ _ %+ %1)
- global %1
+ %ifidn __OUTPUT_FORMAT__,elf
+ global %1:data hidden
+ %else
+ global %1
+ %endif
%1: %2
%endmacro
@@ -735,12 +751,10 @@ SECTION .note.GNU-stack noalloc noexec nowrite progbits
%assign cpuflags_cache64 (1<<17)
%assign cpuflags_slowctz (1<<18)
%assign cpuflags_lzcnt (1<<19)
-%assign cpuflags_misalign (1<<20)
-%assign cpuflags_aligned (1<<21) ; not a cpu feature, but a function variant
-%assign cpuflags_atom (1<<22)
-%assign cpuflags_bmi1 (1<<23)
-%assign cpuflags_bmi2 (1<<24)|cpuflags_bmi1
-%assign cpuflags_tbm (1<<25)|cpuflags_bmi1
+%assign cpuflags_aligned (1<<20) ; not a cpu feature, but a function variant
+%assign cpuflags_atom (1<<21)
+%assign cpuflags_bmi1 (1<<22)|cpuflags_lzcnt
+%assign cpuflags_bmi2 (1<<23)|cpuflags_bmi1
%define cpuflag(x) ((cpuflags & (cpuflags_ %+ x)) == (cpuflags_ %+ x))
%define notcpuflag(x) ((cpuflags & (cpuflags_ %+ x)) != (cpuflags_ %+ x))
@@ -761,7 +775,7 @@ SECTION .note.GNU-stack noalloc noexec nowrite progbits
%if cpuflag(avx)
%assign avx_enabled 1
%endif
- %if mmsize == 16 && notcpuflag(sse2)
+ %if (mmsize == 16 && notcpuflag(sse2)) || (mmsize == 32 && notcpuflag(avx2))
%define mova movaps
%define movu movups
%define movnta movntps
@@ -781,7 +795,11 @@ SECTION .note.GNU-stack noalloc noexec nowrite progbits
%endif
%endmacro
-; merge mmx and sse*
+; Merge mmx and sse*
+; m# is a simd regsiter of the currently selected size
+; xm# is the corresponding xmmreg (if selcted xmm or ymm size), or mmreg (if selected mmx)
+; ym# is the corresponding ymmreg (if selcted xmm or ymm size), or mmreg (if selected mmx)
+; (All 3 remain in sync through SWAP.)
%macro CAT_XDEFINE 3
%xdefine %1%2 %3
@@ -851,10 +869,10 @@ SECTION .note.GNU-stack noalloc noexec nowrite progbits
%if ARCH_X86_64
%define num_mmregs 16
%endif
- %define mova vmovaps
- %define movu vmovups
+ %define mova movdqa
+ %define movu movdqu
%undef movh
- %define movnta vmovntps
+ %define movnta movntdq
%assign %%i 0
%rep num_mmregs
CAT_XDEFINE m, %%i, ymm %+ %%i
@@ -866,6 +884,26 @@ SECTION .note.GNU-stack noalloc noexec nowrite progbits
INIT_XMM
+%macro DECLARE_MMCAST 1
+ %define mmmm%1 mm%1
+ %define mmxmm%1 mm%1
+ %define mmymm%1 mm%1
+ %define xmmmm%1 mm%1
+ %define xmmxmm%1 xmm%1
+ %define xmmymm%1 xmm%1
+ %define ymmmm%1 mm%1
+ %define ymmxmm%1 ymm%1
+ %define ymmymm%1 ymm%1
+ %define xm%1 xmm %+ m%1
+ %define ym%1 ymm %+ m%1
+%endmacro
+
+%assign i 0
+%rep 16
+ DECLARE_MMCAST i
+%assign i i+1
+%endrep
+
; I often want to use macros that permute their arguments. e.g. there's no
; efficient way to implement butterfly or transpose or dct without swapping some
; arguments.
@@ -882,42 +920,42 @@ INIT_XMM
%macro PERMUTE 2-* ; takes a list of pairs to swap
%rep %0/2
- %xdefine tmp%2 m%2
- %xdefine ntmp%2 nm%2
+ %xdefine %%tmp%2 m%2
%rotate 2
%endrep
%rep %0/2
- %xdefine m%1 tmp%2
- %xdefine nm%1 ntmp%2
- %undef tmp%2
- %undef ntmp%2
+ %xdefine m%1 %%tmp%2
+ CAT_XDEFINE n, m%1, %1
%rotate 2
%endrep
%endmacro
-%macro SWAP 2-* ; swaps a single chain (sometimes more concise than pairs)
-%rep %0-1
-%ifdef m%1
- %xdefine tmp m%1
- %xdefine m%1 m%2
- %xdefine m%2 tmp
- CAT_XDEFINE n, m%1, %1
- CAT_XDEFINE n, m%2, %2
-%else
- ; If we were called as "SWAP m0,m1" rather than "SWAP 0,1" infer the original numbers here.
- ; Be careful using this mode in nested macros though, as in some cases there may be
- ; other copies of m# that have already been dereferenced and don't get updated correctly.
- %xdefine %%n1 n %+ %1
- %xdefine %%n2 n %+ %2
- %xdefine tmp m %+ %%n1
- CAT_XDEFINE m, %%n1, m %+ %%n2
- CAT_XDEFINE m, %%n2, tmp
- CAT_XDEFINE n, m %+ %%n1, %%n1
- CAT_XDEFINE n, m %+ %%n2, %%n2
+%macro SWAP 2+ ; swaps a single chain (sometimes more concise than pairs)
+%ifnum %1 ; SWAP 0, 1, ...
+ SWAP_INTERNAL_NUM %1, %2
+%else ; SWAP m0, m1, ...
+ SWAP_INTERNAL_NAME %1, %2
%endif
- %undef tmp
+%endmacro
+
+%macro SWAP_INTERNAL_NUM 2-*
+ %rep %0-1
+ %xdefine %%tmp m%1
+ %xdefine m%1 m%2
+ %xdefine m%2 %%tmp
+ CAT_XDEFINE n, m%1, %1
+ CAT_XDEFINE n, m%2, %2
%rotate 1
-%endrep
+ %endrep
+%endmacro
+
+%macro SWAP_INTERNAL_NAME 2-*
+ %xdefine %%args n %+ %1
+ %rep %0-1
+ %xdefine %%args %%args, n %+ %2
+ %rotate 1
+ %endrep
+ SWAP_INTERNAL_NUM %%args
%endmacro
; If SAVE_MM_PERMUTATION is placed at the end of a function, then any later
@@ -1015,122 +1053,148 @@ INIT_XMM
;%1 == instruction
;%2 == 1 if float, 0 if int
-;%3 == 1 if 4-operand (xmm, xmm, xmm, imm), 0 if 2- or 3-operand (xmm, xmm, xmm)
-;%4 == number of operands given
+;%3 == 1 if non-destructive or 4-operand (xmm, xmm, xmm, imm), 0 otherwise
+;%4 == 1 if commutative (i.e. doesn't matter which src arg is which), 0 if not
;%5+: operands
-%macro RUN_AVX_INSTR 6-7+
- %ifid %6
- %define %%sizeofreg sizeof%6
- %elifid %5
- %define %%sizeofreg sizeof%5
+%macro RUN_AVX_INSTR 5-8+
+ %ifnum sizeof%6
+ %assign %%sizeofreg sizeof%6
+ %elifnum sizeof%5
+ %assign %%sizeofreg sizeof%5
%else
- %define %%sizeofreg mmsize
+ %assign %%sizeofreg mmsize
%endif
- %if %%sizeofreg==32
- %if %4>=3
- v%1 %5, %6, %7
- %else
- v%1 %5, %6
- %endif
+ %assign %%emulate_avx 0
+ %if avx_enabled && %%sizeofreg >= 16
+ %xdefine %%instr v%1
%else
- %if %%sizeofreg==8
- %define %%regmov movq
- %elif %2
- %define %%regmov movaps
- %else
- %define %%regmov movdqa
+ %xdefine %%instr %1
+ %if %0 >= 7+%3
+ %assign %%emulate_avx 1
%endif
+ %endif
- %if %4>=3+%3
- %ifnidn %5, %6
- %if avx_enabled && %%sizeofreg==16
- v%1 %5, %6, %7
- %else
- CHECK_AVX_INSTR_EMU {%1 %5, %6, %7}, %5, %7
- %%regmov %5, %6
- %1 %5, %7
+ %if %%emulate_avx
+ %xdefine %%src1 %6
+ %xdefine %%src2 %7
+ %ifnidn %5, %6
+ %if %0 >= 8
+ CHECK_AVX_INSTR_EMU {%1 %5, %6, %7, %8}, %5, %7, %8
+ %else
+ CHECK_AVX_INSTR_EMU {%1 %5, %6, %7}, %5, %7
+ %endif
+ %if %4 && %3 == 0
+ %ifnid %7
+ ; 3-operand AVX instructions with a memory arg can only have it in src2,
+ ; whereas SSE emulation prefers to have it in src1 (i.e. the mov).
+ ; So, if the instruction is commutative with a memory arg, swap them.
+ %xdefine %%src1 %7
+ %xdefine %%src2 %6
%endif
+ %endif
+ %if %%sizeofreg == 8
+ MOVQ %5, %%src1
+ %elif %2
+ MOVAPS %5, %%src1
%else
- %1 %5, %7
+ MOVDQA %5, %%src1
%endif
- %elif %4>=3
- %1 %5, %6, %7
- %else
- %1 %5, %6
- %endif
- %endif
-%endmacro
-
-; 3arg AVX ops with a memory arg can only have it in src2,
-; whereas SSE emulation of 3arg prefers to have it in src1 (i.e. the mov).
-; So, if the op is symmetric and the wrong one is memory, swap them.
-%macro RUN_AVX_INSTR1 8
- %assign %%swap 0
- %if avx_enabled
- %ifnid %6
- %assign %%swap 1
%endif
- %elifnidn %5, %6
- %ifnid %7
- %assign %%swap 1
+ %if %0 >= 8
+ %1 %5, %%src2, %8
+ %else
+ %1 %5, %%src2
%endif
- %endif
- %if %%swap && %3 == 0 && %8 == 1
- RUN_AVX_INSTR %1, %2, %3, %4, %5, %7, %6
+ %elif %0 >= 8
+ %%instr %5, %6, %7, %8
+ %elif %0 == 7
+ %%instr %5, %6, %7
+ %elif %0 == 6
+ %%instr %5, %6
%else
- RUN_AVX_INSTR %1, %2, %3, %4, %5, %6, %7
+ %%instr %5
%endif
%endmacro
;%1 == instruction
;%2 == 1 if float, 0 if int
-;%3 == 1 if 4-operand (xmm, xmm, xmm, imm), 0 if 2- or 3-operand (xmm, xmm, xmm)
-;%4 == 1 if symmetric (i.e. doesn't matter which src arg is which), 0 if not
-%macro AVX_INSTR 4
- %macro %1 2-9 fnord, fnord, fnord, %1, %2, %3, %4
- %ifidn %3, fnord
- RUN_AVX_INSTR %6, %7, %8, 2, %1, %2
+;%3 == 1 if non-destructive or 4-operand (xmm, xmm, xmm, imm), 0 otherwise
+;%4 == 1 if commutative (i.e. doesn't matter which src arg is which), 0 if not
+%macro AVX_INSTR 1-4 0, 1, 0
+ %macro %1 1-9 fnord, fnord, fnord, fnord, %1, %2, %3, %4
+ %ifidn %2, fnord
+ RUN_AVX_INSTR %6, %7, %8, %9, %1
+ %elifidn %3, fnord
+ RUN_AVX_INSTR %6, %7, %8, %9, %1, %2
%elifidn %4, fnord
- RUN_AVX_INSTR1 %6, %7, %8, 3, %1, %2, %3, %9
+ RUN_AVX_INSTR %6, %7, %8, %9, %1, %2, %3
%elifidn %5, fnord
- RUN_AVX_INSTR %6, %7, %8, 4, %1, %2, %3, %4
+ RUN_AVX_INSTR %6, %7, %8, %9, %1, %2, %3, %4
%else
- RUN_AVX_INSTR %6, %7, %8, 5, %1, %2, %3, %4, %5
+ RUN_AVX_INSTR %6, %7, %8, %9, %1, %2, %3, %4, %5
%endif
%endmacro
%endmacro
+; Instructions with both VEX and non-VEX encodings
+; Non-destructive instructions are written without parameters
AVX_INSTR addpd, 1, 0, 1
AVX_INSTR addps, 1, 0, 1
AVX_INSTR addsd, 1, 0, 1
AVX_INSTR addss, 1, 0, 1
AVX_INSTR addsubpd, 1, 0, 0
AVX_INSTR addsubps, 1, 0, 0
-AVX_INSTR andpd, 1, 0, 1
-AVX_INSTR andps, 1, 0, 1
+AVX_INSTR aesdec, 0, 0, 0
+AVX_INSTR aesdeclast, 0, 0, 0
+AVX_INSTR aesenc, 0, 0, 0
+AVX_INSTR aesenclast, 0, 0, 0
+AVX_INSTR aesimc
+AVX_INSTR aeskeygenassist
AVX_INSTR andnpd, 1, 0, 0
AVX_INSTR andnps, 1, 0, 0
+AVX_INSTR andpd, 1, 0, 1
+AVX_INSTR andps, 1, 0, 1
AVX_INSTR blendpd, 1, 0, 0
AVX_INSTR blendps, 1, 0, 0
AVX_INSTR blendvpd, 1, 0, 0
AVX_INSTR blendvps, 1, 0, 0
-AVX_INSTR cmppd, 1, 0, 0
-AVX_INSTR cmpps, 1, 0, 0
-AVX_INSTR cmpsd, 1, 0, 0
-AVX_INSTR cmpss, 1, 0, 0
-AVX_INSTR cvtdq2ps, 1, 0, 0
-AVX_INSTR cvtpd2dq, 1, 0, 0
-AVX_INSTR cvtps2dq, 1, 0, 0
+AVX_INSTR cmppd, 1, 1, 0
+AVX_INSTR cmpps, 1, 1, 0
+AVX_INSTR cmpsd, 1, 1, 0
+AVX_INSTR cmpss, 1, 1, 0
+AVX_INSTR comisd
+AVX_INSTR comiss
+AVX_INSTR cvtdq2pd
+AVX_INSTR cvtdq2ps
+AVX_INSTR cvtpd2dq
+AVX_INSTR cvtpd2ps
+AVX_INSTR cvtps2dq
+AVX_INSTR cvtps2pd
+AVX_INSTR cvtsd2si
+AVX_INSTR cvtsd2ss
+AVX_INSTR cvtsi2sd
+AVX_INSTR cvtsi2ss
+AVX_INSTR cvtss2sd
+AVX_INSTR cvtss2si
+AVX_INSTR cvttpd2dq
+AVX_INSTR cvttps2dq
+AVX_INSTR cvttsd2si
+AVX_INSTR cvttss2si
AVX_INSTR divpd, 1, 0, 0
AVX_INSTR divps, 1, 0, 0
AVX_INSTR divsd, 1, 0, 0
AVX_INSTR divss, 1, 0, 0
AVX_INSTR dppd, 1, 1, 0
AVX_INSTR dpps, 1, 1, 0
+AVX_INSTR extractps
AVX_INSTR haddpd, 1, 0, 0
AVX_INSTR haddps, 1, 0, 0
AVX_INSTR hsubpd, 1, 0, 0
AVX_INSTR hsubps, 1, 0, 0
+AVX_INSTR insertps, 1, 1, 0
+AVX_INSTR lddqu
+AVX_INSTR ldmxcsr
+AVX_INSTR maskmovdqu
AVX_INSTR maxpd, 1, 0, 1
AVX_INSTR maxps, 1, 0, 1
AVX_INSTR maxsd, 1, 0, 1
@@ -1139,10 +1203,31 @@ AVX_INSTR minpd, 1, 0, 1
AVX_INSTR minps, 1, 0, 1
AVX_INSTR minsd, 1, 0, 1
AVX_INSTR minss, 1, 0, 1
+AVX_INSTR movapd
+AVX_INSTR movaps
+AVX_INSTR movd
+AVX_INSTR movddup
+AVX_INSTR movdqa
+AVX_INSTR movdqu
AVX_INSTR movhlps, 1, 0, 0
+AVX_INSTR movhpd, 1, 0, 0
+AVX_INSTR movhps, 1, 0, 0
AVX_INSTR movlhps, 1, 0, 0
+AVX_INSTR movlpd, 1, 0, 0
+AVX_INSTR movlps, 1, 0, 0
+AVX_INSTR movmskpd
+AVX_INSTR movmskps
+AVX_INSTR movntdq
+AVX_INSTR movntdqa
+AVX_INSTR movntpd
+AVX_INSTR movntps
+AVX_INSTR movq
AVX_INSTR movsd, 1, 0, 0
+AVX_INSTR movshdup
+AVX_INSTR movsldup
AVX_INSTR movss, 1, 0, 0
+AVX_INSTR movupd
+AVX_INSTR movups
AVX_INSTR mpsadbw, 0, 1, 0
AVX_INSTR mulpd, 1, 0, 1
AVX_INSTR mulps, 1, 0, 1
@@ -1150,9 +1235,9 @@ AVX_INSTR mulsd, 1, 0, 1
AVX_INSTR mulss, 1, 0, 1
AVX_INSTR orpd, 1, 0, 1
AVX_INSTR orps, 1, 0, 1
-AVX_INSTR pabsb, 0, 0, 0
-AVX_INSTR pabsw, 0, 0, 0
-AVX_INSTR pabsd, 0, 0, 0
+AVX_INSTR pabsb
+AVX_INSTR pabsd
+AVX_INSTR pabsw
AVX_INSTR packsswb, 0, 0, 0
AVX_INSTR packssdw, 0, 0, 0
AVX_INSTR packuswb, 0, 0, 0
@@ -1172,10 +1257,11 @@ AVX_INSTR pavgb, 0, 0, 1
AVX_INSTR pavgw, 0, 0, 1
AVX_INSTR pblendvb, 0, 0, 0
AVX_INSTR pblendw, 0, 1, 0
-AVX_INSTR pcmpestri, 0, 0, 0
-AVX_INSTR pcmpestrm, 0, 0, 0
-AVX_INSTR pcmpistri, 0, 0, 0
-AVX_INSTR pcmpistrm, 0, 0, 0
+AVX_INSTR pclmulqdq, 0, 1, 0
+AVX_INSTR pcmpestri
+AVX_INSTR pcmpestrm
+AVX_INSTR pcmpistri
+AVX_INSTR pcmpistrm
AVX_INSTR pcmpeqb, 0, 0, 1
AVX_INSTR pcmpeqw, 0, 0, 1
AVX_INSTR pcmpeqd, 0, 0, 1
@@ -1184,12 +1270,21 @@ AVX_INSTR pcmpgtb, 0, 0, 0
AVX_INSTR pcmpgtw, 0, 0, 0
AVX_INSTR pcmpgtd, 0, 0, 0
AVX_INSTR pcmpgtq, 0, 0, 0
+AVX_INSTR pextrb
+AVX_INSTR pextrd
+AVX_INSTR pextrq
+AVX_INSTR pextrw
AVX_INSTR phaddw, 0, 0, 0
AVX_INSTR phaddd, 0, 0, 0
AVX_INSTR phaddsw, 0, 0, 0
+AVX_INSTR phminposuw
AVX_INSTR phsubw, 0, 0, 0
AVX_INSTR phsubd, 0, 0, 0
AVX_INSTR phsubsw, 0, 0, 0
+AVX_INSTR pinsrb, 0, 1, 0
+AVX_INSTR pinsrd, 0, 1, 0
+AVX_INSTR pinsrq, 0, 1, 0
+AVX_INSTR pinsrw, 0, 1, 0
AVX_INSTR pmaddwd, 0, 0, 1
AVX_INSTR pmaddubsw, 0, 0, 0
AVX_INSTR pmaxsb, 0, 0, 1
@@ -1204,20 +1299,32 @@ AVX_INSTR pminsd, 0, 0, 1
AVX_INSTR pminub, 0, 0, 1
AVX_INSTR pminuw, 0, 0, 1
AVX_INSTR pminud, 0, 0, 1
-AVX_INSTR pmovmskb, 0, 0, 0
-AVX_INSTR pmulhuw, 0, 0, 1
+AVX_INSTR pmovmskb
+AVX_INSTR pmovsxbw
+AVX_INSTR pmovsxbd
+AVX_INSTR pmovsxbq
+AVX_INSTR pmovsxwd
+AVX_INSTR pmovsxwq
+AVX_INSTR pmovsxdq
+AVX_INSTR pmovzxbw
+AVX_INSTR pmovzxbd
+AVX_INSTR pmovzxbq
+AVX_INSTR pmovzxwd
+AVX_INSTR pmovzxwq
+AVX_INSTR pmovzxdq
+AVX_INSTR pmuldq, 0, 0, 1
AVX_INSTR pmulhrsw, 0, 0, 1
+AVX_INSTR pmulhuw, 0, 0, 1
AVX_INSTR pmulhw, 0, 0, 1
AVX_INSTR pmullw, 0, 0, 1
AVX_INSTR pmulld, 0, 0, 1
AVX_INSTR pmuludq, 0, 0, 1
-AVX_INSTR pmuldq, 0, 0, 1
AVX_INSTR por, 0, 0, 1
AVX_INSTR psadbw, 0, 0, 1
AVX_INSTR pshufb, 0, 0, 0
-AVX_INSTR pshufd, 0, 1, 0
-AVX_INSTR pshufhw, 0, 1, 0
-AVX_INSTR pshuflw, 0, 1, 0
+AVX_INSTR pshufd
+AVX_INSTR pshufhw
+AVX_INSTR pshuflw
AVX_INSTR psignb, 0, 0, 0
AVX_INSTR psignw, 0, 0, 0
AVX_INSTR psignd, 0, 0, 0
@@ -1239,7 +1346,7 @@ AVX_INSTR psubsb, 0, 0, 0
AVX_INSTR psubsw, 0, 0, 0
AVX_INSTR psubusb, 0, 0, 0
AVX_INSTR psubusw, 0, 0, 0
-AVX_INSTR ptest, 0, 0, 0
+AVX_INSTR ptest
AVX_INSTR punpckhbw, 0, 0, 0
AVX_INSTR punpckhwd, 0, 0, 0
AVX_INSTR punpckhdq, 0, 0, 0
@@ -1249,11 +1356,27 @@ AVX_INSTR punpcklwd, 0, 0, 0
AVX_INSTR punpckldq, 0, 0, 0
AVX_INSTR punpcklqdq, 0, 0, 0
AVX_INSTR pxor, 0, 0, 1
+AVX_INSTR rcpps, 1, 0, 0
+AVX_INSTR rcpss, 1, 0, 0
+AVX_INSTR roundpd
+AVX_INSTR roundps
+AVX_INSTR roundsd
+AVX_INSTR roundss
+AVX_INSTR rsqrtps, 1, 0, 0
+AVX_INSTR rsqrtss, 1, 0, 0
+AVX_INSTR shufpd, 1, 1, 0
AVX_INSTR shufps, 1, 1, 0
+AVX_INSTR sqrtpd, 1, 0, 0
+AVX_INSTR sqrtps, 1, 0, 0
+AVX_INSTR sqrtsd, 1, 0, 0
+AVX_INSTR sqrtss, 1, 0, 0
+AVX_INSTR stmxcsr
AVX_INSTR subpd, 1, 0, 0
AVX_INSTR subps, 1, 0, 0
AVX_INSTR subsd, 1, 0, 0
AVX_INSTR subss, 1, 0, 0
+AVX_INSTR ucomisd
+AVX_INSTR ucomiss
AVX_INSTR unpckhpd, 1, 0, 0
AVX_INSTR unpckhps, 1, 0, 0
AVX_INSTR unpcklpd, 1, 0, 0
@@ -1285,22 +1408,16 @@ AVX_INSTR pfmul, 1, 0, 1
%undef j
%macro FMA_INSTR 3
- %macro %1 5-8 %1, %2, %3
- %if cpuflag(xop) || cpuflag(fma4)
- v%6 %1, %2, %3, %4
+ %macro %1 4-7 %1, %2, %3
+ %if cpuflag(xop)
+ v%5 %1, %2, %3, %4
%else
- %ifidn %1, %4
- %7 %5, %2, %3
- %8 %1, %4, %5
- %else
- %7 %1, %2, %3
- %8 %1, %4
- %endif
+ %6 %1, %2, %3
+ %7 %1, %4
%endif
%endmacro
%endmacro
-FMA_INSTR fmaddps, mulps, addps
FMA_INSTR pmacsdd, pmulld, paddd
FMA_INSTR pmacsww, pmullw, paddw
FMA_INSTR pmadcswd, pmaddwd, paddd
@@ -1308,3 +1425,56 @@ FMA_INSTR pmadcswd, pmaddwd, paddd
; tzcnt is equivalent to "rep bsf" and is backwards-compatible with bsf.
; This lets us use tzcnt without bumping the yasm version requirement yet.
%define tzcnt rep bsf
+
+; convert FMA4 to FMA3 if possible
+%macro FMA4_INSTR 4
+ %macro %1 4-8 %1, %2, %3, %4
+ %if cpuflag(fma4)
+ v%5 %1, %2, %3, %4
+ %elifidn %1, %2
+ v%6 %1, %4, %3 ; %1 = %1 * %3 + %4
+ %elifidn %1, %3
+ v%7 %1, %2, %4 ; %1 = %2 * %1 + %4
+ %elifidn %1, %4
+ v%8 %1, %2, %3 ; %1 = %2 * %3 + %1
+ %else
+ %error fma3 emulation of ``%5 %1, %2, %3, %4'' is not supported
+ %endif
+ %endmacro
+%endmacro
+
+FMA4_INSTR fmaddpd, fmadd132pd, fmadd213pd, fmadd231pd
+FMA4_INSTR fmaddps, fmadd132ps, fmadd213ps, fmadd231ps
+FMA4_INSTR fmaddsd, fmadd132sd, fmadd213sd, fmadd231sd
+FMA4_INSTR fmaddss, fmadd132ss, fmadd213ss, fmadd231ss
+
+FMA4_INSTR fmaddsubpd, fmaddsub132pd, fmaddsub213pd, fmaddsub231pd
+FMA4_INSTR fmaddsubps, fmaddsub132ps, fmaddsub213ps, fmaddsub231ps
+FMA4_INSTR fmsubaddpd, fmsubadd132pd, fmsubadd213pd, fmsubadd231pd
+FMA4_INSTR fmsubaddps, fmsubadd132ps, fmsubadd213ps, fmsubadd231ps
+
+FMA4_INSTR fmsubpd, fmsub132pd, fmsub213pd, fmsub231pd
+FMA4_INSTR fmsubps, fmsub132ps, fmsub213ps, fmsub231ps
+FMA4_INSTR fmsubsd, fmsub132sd, fmsub213sd, fmsub231sd
+FMA4_INSTR fmsubss, fmsub132ss, fmsub213ss, fmsub231ss
+
+FMA4_INSTR fnmaddpd, fnmadd132pd, fnmadd213pd, fnmadd231pd
+FMA4_INSTR fnmaddps, fnmadd132ps, fnmadd213ps, fnmadd231ps
+FMA4_INSTR fnmaddsd, fnmadd132sd, fnmadd213sd, fnmadd231sd
+FMA4_INSTR fnmaddss, fnmadd132ss, fnmadd213ss, fnmadd231ss
+
+FMA4_INSTR fnmsubpd, fnmsub132pd, fnmsub213pd, fnmsub231pd
+FMA4_INSTR fnmsubps, fnmsub132ps, fnmsub213ps, fnmsub231ps
+FMA4_INSTR fnmsubsd, fnmsub132sd, fnmsub213sd, fnmsub231sd
+FMA4_INSTR fnmsubss, fnmsub132ss, fnmsub213ss, fnmsub231ss
+
+; workaround: vpbroadcastq is broken in x86_32 due to a yasm bug
+%if ARCH_X86_64 == 0
+%macro vpbroadcastq 2
+%if sizeof%1 == 16
+ movddup %1, %2
+%else
+ vbroadcastsd %1, %2
+%endif
+%endmacro
+%endif
diff --git a/ffmpeg/libavutil/x86/x86util.asm b/ffmpeg/libavutil/x86/x86util.asm
index 8908444..59e5df2 100644
--- a/ffmpeg/libavutil/x86/x86util.asm
+++ b/ffmpeg/libavutil/x86/x86util.asm
@@ -665,3 +665,16 @@
psrad %1, 16
%endif
%endmacro
+
+; Wrapper for non-FMA version of fmaddps
+%macro FMULADD_PS 5
+ %if cpuflag(fma3) || cpuflag(fma4)
+ fmaddps %1, %2, %3, %4
+ %elifidn %1, %4
+ mulps %5, %2, %3
+ addps %1, %4, %5
+ %else
+ mulps %1, %2, %3
+ addps %1, %4
+ %endif
+%endmacro
generated by cgit v1.2.3 (git 2.39.1) at 2025-12-06 15:59:44 +0000